The functional correctness of semiconductor memory devices is extremely important in computer technology. Accordingly, a memory device is tested often throughout its life in order to reduce the possibility of unexpected failure at a critical moment. Specifically, the overall goal of memory testing is to insure that the memory holds a variety of patterns and to insure that the address of each location is unique and correct.
It is difficult to maintain image (data) correctness stored in a non-volatile random access memory (NVRAM) when a disruption of testing activity occurs during the testing process. However, a complete and accurate image must be maintained even if power fails or the test is interrupted. The goal of retaining the image is particularly important since it may contain cached data that has not been stored on hardened media.
Generally, in prior art systems, the RAM is either left not tested or is left subject to potential data loss or corruption if a disruption occurs during testing. Therefore, to overcome the potential for data loss or corruption (i.e., to protect the memory image) during testing, some systems use multiple banks of NVRAM to hold the image of one of the banks being tested. However, this use of extra hardware components (additional NVRAM) increases the cost of the system.
Other systems copy the memory image to an available register memory such as typically exists in a microprocessor. However, in the event of a powerfail, the register memory is susceptible to data loss unless it is non-volatile, which increases the cost of the device.
Accordingly, objects of the present invention are to provide a cost-effective method for providing powerfail durable NVRAM testing without the need for additional memory banks or other specialized hardware.